This invention relates to semiconductor devices and methods of manufacture thereof, and more particularly to an improved contact and interconnect arrangement for N-channel, silicon-gate MOS integrated circuits of the type having double-level polycrystalline silicon structures.
MOS integrated circuits employing double-level polysilicon processes are disclosed in prior pending applications as follows, all assigned to Texas Instruments:
Ser. No. 648,594, filed Jan. 12, 1976 by C-K Kuo PA1 Ser. No. 722,841, filed Sept. 13, 1976 by C-K Kuo PA1 Ser. No. 754,144, filed Dec. 27, 1976 by L. S. Wall PA1 Ser. No. 762,613, filed Jan. 26, 1977 by D. J. McElroy
In addition, a double-level poly structure is shown in Electronics, Feb. 19, 1976, pp. 116-121.
The prior semiconductor manufacturing methods have used second-level polycrystalline silicon with its underlying gate oxide as a diffusion mask to create the N+ diffused regions in N-channel, silicon-gate MOS devices. This has limited the utility of the various levels as interconnects, and contacts between the levels has been restricted. Supposedly, in a double-level poly structure, there are four interconnect levels: N+ moat; first level poly; second level poly; metallization. However, with prior methods, the second level poly could not cross an N+ moat region as it was the diffusion mask, i.e., created a transistor when it crossed a moat. Also, metal to moat contacts were not readily made due to the step caused by the thicknesses of the several layers and the interleaved insulators.
It is therefore the principal object of the invention to provide an improved N-channel silicon-gate semiconductor device and method of manufacture. Another object is to provide an improved contact and interconnect arrangement for integrated circuits.